{
    "dataType": "CVE_RECORD",
    "dataVersion": "5.2",
    "cveMetadata": {
        "cveId": "CVE-2026-50185",
        "assignerOrgId": "a0819718-46f1-4df5-94e2-005712e83aaa",
        "state": "PUBLISHED",
        "assignerShortName": "GitHub_M",
        "dateReserved": "2026-06-03T22:05:13.644Z",
        "datePublished": "2026-07-17T18:35:02.078Z",
        "dateUpdated": "2026-07-20T19:24:54.587Z"
    },
    "containers": {
        "cna": {
            "title": "RustCrypto Cmov/CmovEq on aarch64 can produce wrong results if high-bits of registers are set",
            "problemTypes": [
                {
                    "descriptions": [
                        {
                            "cweId": "CWE-758",
                            "lang": "en",
                            "description": "CWE-758: Reliance on Undefined, Unspecified, or Implementation-Defined Behavior",
                            "type": "CWE"
                        }
                    ]
                }
            ],
            "metrics": [
                {
                    "cvssV4_0": {
                        "attackVector": "LOCAL",
                        "attackComplexity": "LOW",
                        "attackRequirements": "PRESENT",
                        "privilegesRequired": "LOW",
                        "userInteraction": "NONE",
                        "vulnConfidentialityImpact": "NONE",
                        "vulnIntegrityImpact": "LOW",
                        "vulnAvailabilityImpact": "NONE",
                        "subConfidentialityImpact": "NONE",
                        "subIntegrityImpact": "NONE",
                        "subAvailabilityImpact": "NONE",
                        "baseScore": 2,
                        "baseSeverity": "LOW",
                        "vectorString": "CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:N/VC:N/VI:L/VA:N/SC:N/SI:N/SA:N",
                        "version": "4.0"
                    }
                }
            ],
            "references": [
                {
                    "name": "https://github.com/RustCrypto/utils/security/advisories/GHSA-3rjw-m598-pq24",
                    "tags": [
                        "x_refsource_CONFIRM"
                    ],
                    "url": "https://github.com/RustCrypto/utils/security/advisories/GHSA-3rjw-m598-pq24"
                },
                {
                    "name": "https://github.com/RustCrypto/utils/commit/dba6c355c9f241e3726d5ec2a68f9f3b519f6063",
                    "tags": [
                        "x_refsource_MISC"
                    ],
                    "url": "https://github.com/RustCrypto/utils/commit/dba6c355c9f241e3726d5ec2a68f9f3b519f6063"
                },
                {
                    "name": "https://github.com/RustCrypto/utils/releases/tag/cmov-v0.5.4",
                    "tags": [
                        "x_refsource_MISC"
                    ],
                    "url": "https://github.com/RustCrypto/utils/releases/tag/cmov-v0.5.4"
                }
            ],
            "affected": [
                {
                    "vendor": "RustCrypto",
                    "product": "utils",
                    "versions": [
                        {
                            "version": ">= 0.1.1, < 0.5.4",
                            "status": "affected"
                        }
                    ]
                }
            ],
            "providerMetadata": {
                "orgId": "a0819718-46f1-4df5-94e2-005712e83aaa",
                "shortName": "GitHub_M",
                "dateUpdated": "2026-07-17T18:35:02.078Z"
            },
            "descriptions": [
                {
                    "lang": "en",
                    "value": "RustCrypto CMOV provides conditional move CPU intrinsics which are guaranteed on major platforms to execute in constant-time and not be rewritten as branches by the compiler. From 0.1.1 until 0.5.4, the aarch64 implementations of Cmov and CmovEq in cmov/src/backends/aarch64.rs assume high bits are zero-extended when loading values smaller than a register, so set high bits such as [8..] in a Cmov selector or [16..] of self or other in the u16 and i16 CmovEq implementations can cause left.cmovz(&right, condition) to produce incorrect output. This issue is fixed in version 0.5.4."
                }
            ],
            "source": {
                "advisory": "GHSA-3rjw-m598-pq24",
                "discovery": "UNKNOWN"
            }
        },
        "adp": [
            {
                "references": [
                    {
                        "url": "https://github.com/RustCrypto/utils/security/advisories/GHSA-3rjw-m598-pq24",
                        "tags": [
                            "exploit"
                        ]
                    }
                ],
                "metrics": [
                    {
                        "other": {
                            "type": "ssvc",
                            "content": {
                                "timestamp": "2026-07-20T19:24:50.398494Z",
                                "id": "CVE-2026-50185",
                                "options": [
                                    {
                                        "Exploitation": "poc"
                                    },
                                    {
                                        "Automatable": "no"
                                    },
                                    {
                                        "Technical Impact": "partial"
                                    }
                                ],
                                "role": "CISA Coordinator",
                                "version": "2.0.3"
                            }
                        }
                    }
                ],
                "title": "CISA ADP Vulnrichment",
                "providerMetadata": {
                    "orgId": "134c704f-9b21-4f2e-91b3-4a467353bcc0",
                    "shortName": "CISA-ADP",
                    "dateUpdated": "2026-07-20T19:24:54.587Z"
                }
            }
        ]
    }
}